The invention relates to memory devices for high performance computers and more specifically to high density structures constructed of a plurality of discrete integrated circuit chips, such as integrated circuit memory chips, stacked in a three dimensional fashion.
High density integrated circuit memory chips are known which include a stack of on the order of four to forty semiconductor memory chips. The memory chips are typically of a substantially square configuration and are joined together by an appropriate adhesive in a stacked configuration to form a parallelepiped structure referred to as a memory cube. Each memory chip typically has surface contact metalization on at least one side to provide for connections to the chip. The memory chips are arranged in the cube to allow for interconnections along one or more of the faces of the resulting memory cube. The cube is typically mounted on a printed circuit substrate to provide for external connections to the memory, as depicted in the prior art arrangement shown in FIG. 1.
Stacked integrated circuit packaging structures have been shown to be particularly advantageous for high performance computers. They provide high packaging densities and easier access for interconnections. They are simplified manufacturing processes at reduced costs, while providing improved structural strength.
The high-speed memory arrays typically consist of CMOS VLSI chips having large numbers of gates on each chip. A problem with densely packed, high-speed memory devices is the signal interference or "noise" which occurs when the memory is accessed to read data from or write data into the individual memory arrays. Particularly, every time one of the many gates of the chip is switched, as in response to a memory select signal, it tends to produce a current spike on the power bus and the cumulative effect is to cause troublesome transient spikes on the power supply bus which may affect circuit operation. Similarly, simultaneous switching of output drivers during memory read operations causes power supply transients due to the series inductance of the packaging structure. Furthermore, ringing or transmission line noise due to lack of proper terminating circuits at the memory cube causes performance loss for the signal transmitting driver circuits. These noise problems are generally understood and can be solved by providing additional noise limiting circuit elements such as decoupling capacitors and line termination networks. A significant problem in memory design, particularly in the design of high density memory structures such as the memory cube, is the packaging of additional circuit elements which are needed to build a memory which can be accessed at the high rates required for high speed operation.
Additional circuit elements which are typically required in high performance memories include temperature sensing diodes. To assure that the memory chips will operate properly at elevated temperatures, they are tested at high temperatures in what is referred to as a burn-in test. It is difficult to accurately determine the temperature of memory devices under test without internal temperature sensory devices. Since temperature sensing is not required at all chips, the temperature sensing devices are typically not included in the memory chips to keep down the costs of the chips and no inexpensive and accurate means of measuring internal cube temperature is available.
The memory cubes comprise a plurality of silicon integrated circuit chips. For protection of the chip and to provide proper insulation, the silicon chips typically are encapsulated with a passivation layer. They are bonded together by an adhesive applied to the passivation layer. A problem with such a structure is a tendency to crack with large temperature changes due to the difference in coefficient of expansion of the silicon and the passivation and adhesive materials. It is therefore desirable to maintain the structure within a preferred temperature range.
In one known configuration, a memory cube is mounted on a carrier which, in turn, is mounted on a substrate. The basic function of the carrier is to provide connection to discrete decoupling capacitors and terminating networks provided to reduce noise spikes. A problem with that configuration, however, is the added expense and space requirements of a separate carrier. Because of the ever increasing demand for a larger capacity, cheaper memories, both space and manufacturing process expense are criteria which drive to design of memory devices. A major concern in the design of the memory device is to provide effective noise reducing circuitry at a physical location in close proximity to the memory devices. For example, discrete capacitors even a relatively small distance removed from the semiconductor devices become ineffective at high data repetition rates, such as data rates in the 50 to 100 megahertz range occurring during data transfers, particularly for high-band width, large data word memories. Similarly, line terminating networks removed a significant distance from the line terminating point become ineffective. It is therefore desirable to provide decoupling capacitors and line termination devices in close proximity to the integrated circuit devices.